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74LVC2G74 数据手册

型号系列:74LVC2G74 系列
描述:74LVC 系列,NXP低电压 CMOS 逻辑 工作电压:1.2 至 3.6 兼容性:输入 LVTTL/TTL、输出 LVCMOS ### 74LVC 系列
文档:74LVC2G74DC,125 数据手册 (29 )

74LVC2G74 数据手册

#1
74LVC2G74DC,125
1.5
Nexperia(安世)
#2
74LVC2G74GT,115
1.2
NXP(恩智浦)
#3
74LVC2G74GF,115
0.9
NXP(恩智浦)
#4
74LVC2G74DP
2.5
NXP(恩智浦)

74LVC2G74 数据手册

25
NXP(恩智浦)
NXP  74LVC2G74DP,125  触发器, 互补输出, 正沿, D, 200 MHz, 50 mA, TSSOP, 8 引脚
25
Nexperia(安世)
NXP 74LVC2G74DP,125 CMOS 触发器 IC, 单端输出, 1.65 → 5.5 V电源, 8引脚 TSSOP封装
25
Nexperia(安世)
25
Nexperia(安世)
25
NXP(恩智浦)
74LVC 系列 5.5 V 上升沿触发 D型触发器 表面贴装 -XSON-8U
25
NXP(恩智浦)
74LVC 系列 5.5 V 上升沿触发 D型触发器 表面贴装 -VSSOP-8
25
NXP(恩智浦)
25
NXP(恩智浦)
NXP  74LVC2G74GF  触发器, 差分, 正沿, D, 2.5 ns, 200 MHz, 50 mA, XSON, 8 引脚
25
Nexperia(安世)
25
NXP(恩智浦)
25
NXP(恩智浦)
25
Nexperia(安世)
74LVC 系列
20
NXP(恩智浦)
单一的D- FL型IP- FL运算与置位和复位;上升沿触发 Single D-type flip-flop with set and reset; positive edge trigger
18
Nexperia(安世)
18
Nexperia(安世)

74LVC2G74DP - NXP(恩智浦) 技术参数、封装参数

类型
描述
安装方式
Surface Mount
引脚数
8 Pin
封装
SOT-505-2
工作温度(Max)
125 ℃
工作温度(Min)
-40 ℃
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74LVC2G74DP - NXP(恩智浦) 概述

逻辑类型Logic Type| 设置(预设)和复位 Set(Preset) and Reset \---|--- 电路数Number of Circuits| D型 D-Type 输入数Number of Inputs| 差分 Differential 电源电压VccVoltage - Supply| 1 静态电流IqCurrent - Quiescent (Max)| 1 输出高,低电平电流Current - Output High, Low| 200MHz 低逻辑电平Logic Level - Low| 2.5ns 高逻辑电平Logic Level - High| 正边沿 Positive Edge 传播延迟时间@Vcc,CLMax Propagation Delay @ V, Max CL| 32mA,32mA Description & Applications| 1.65 V ~ 5.5 V 描述与应用| Single D-type flip-flop; positive-edge trigger General description The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C.
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