SN74LVC2G74YZPR 数据手册 - TI（德州仪器）

逻辑类型Logic Type| 设置（预设）和复位 Set(Preset) and Reset \---|--- 电路数Number of Circuits| D型 D-Type 输入数Number of Inputs| 差分 Differential 电源电压VccVoltage - Supply| 1 静态电流IqCurrent - Quiescent (Max)| 1 输出高，低电平电流Current - Output High, Low| 200MHz 低逻辑电平Logic Level - Low| 4.1ns 高逻辑电平Logic Level - High| 正边沿 Positive Edge 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL| 32mA，32mA Description & Applications| 1.65 V ~ 5.5 V 描述与应用| SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET DESCRIPTION/ORDERING INFORMATION SN74LVC2G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES203M–APRIL 1999–REVISED FEBRUARY 2007 • Available in the Texas Instruments • Typical VOHV (Output VOH Undershoot) NanoFree™ Package >2 V at VCC = 3.3 V, TA = 25°C • Supports 5-V VCC Operation • I off Supports Partial-Power-Down Mode • Inputs Accept Voltages to 5.5 V Operation • Latch-Up Performance Exceeds 100 mA Per • Max t pd of 5.9 ns at 3.3 V JESD 78, Class II • Low Power Consumption, 10-µA Max ICC • ESD Protection Exceeds JESD 22 • ±24-mA Output Drive at 3.3 V – 2000-V Human-Body Model (A114-A) • Typical VOLP (Output Ground Bounce) <0.8 V at V – 200-V Machine Model (A115-A) CC= 3.3 V, TA= 25°C – 1000-V Charged-Device Model (C101) This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using I off The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. "Available in the Texas Instruments • Typical VOHV (Output VOH Undershoot) NanoFree™ Package >2 V at VCC = 3.3 V, TA = 25°C • Supports 5-V VCC Operation • I off Supports Partial-Power-Down Mode • Inputs Accept Voltages to 5.5 V Operation • Latch-Up Performance Exceeds 100 mA Per • Max tpd of 5.9 ns at 3.3 VJESD 78, Class II • Low Power Consumption, 10-µA Max ICC • ESD Protection Exceeds JESD 22 • ±24-mA Output Drive at 3.3 V – 2000-V Human-Body Model (A114-A) • Typical VOLP (Output Ground Bounce) <0.8 V at V – 200-V Machine Model (A115-A) CC= 3.3 V, TA= 25°C 1000-V Charged-Device Model (C101)"