TC7W74FU 数据手册 - Toshiba（东芝）

逻辑类型Logic Type| 设置（预设）和复位 Set(Preset) and Reset \---|--- 电路数Number of Circuits| D型 D-Type 输入数Number of Inputs| 差分 Differential 电源电压VccVoltage - Supply| 1 静态电流IqCurrent - Quiescent (Max)| 1 输出高，低电平电流Current - Output High, Low| 67MHz 低逻辑电平Logic Level - Low| 13ns 高逻辑电平Logic Level - High| 正边沿 Positive Edge 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL| 5.2mA，5.2mA Description & Applications| 2 V ~ 6 V 描述与应用| D-Type Flip Flop with Preset and Clear The TC7W74 is a high speed C2MOS D Flip Flop fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the C2MOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CLOCK pulse CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the appropriate input to an “L” level Input is equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: fMAX = 77 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH −∼ tpHL • Wide operating voltage range: VCC (opr) = 2 to 6 V